openxiangshan

Analyze OpenXiangShan XiangShan Kunminghu microarchitecture source, design docs, XiangShanLab course concepts, XSCache, chiselAIA,...

Use this skill when analyzing XiangShan/香山 processor simulation waveforms with the wavekit open-source repository. It tracks one i...

Reproduce, diagnose, fix, and validate OpenXiangShan/XiangShan bugs from a GitHub issue number. Use when an agent must drive a fre...

Analyze XiangShan and RISC-V difftest failures from simulator logs plus program BIN, ELF, and objdump/disassembly artifacts. Use w...

Generate illustrated English word learning cards for kids. Activate when the user asks to explain an English word to their daughte...

Extract RISC-V instruction names from a named subsection of an AsciiDoc file and write them to /tmp/<subsection-title>.yaml.

Collect XiangShan GitHub issues and pull requests into a local bug library for triage, branch-aware analysis, and cause summaries.

Look up RISC-V Security Horizontal Committee related specifications, including ratified and unratified/development specs. Activate...

One-stop RISC-V skill pack covering specification learning, gap analysis, requirement analysis, ecosystem governance, and legacy-i...

openxiangshan/xiangshanlab

Generate detailed, code-grounded XiangShan verification scenario descriptions from a microarchitecture optimization mechanism name...

Analyze XiangShan bug waveforms from FST/VCD/FSDB, logs, disassembly, and source. Use when root-causing frontend, backend, Load/St...

End-to-end XiangShan bug pipeline: fetch GitHub issues and PRs, create per-issue bug-analysis-<issue-number> workdirs, build and r...

Generate or update a compact Chisel/Scala DUT that isolates XiangShan MPT checking logic from the full core. Use when working on X...

openxiangshan/xiangshanlab