cao1014/llm_eda/memory-storage

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SKILL.md

memory-storage — SRAM, Cache & Storage Controllers

Overview

Memory subsystem designs including SRAM controllers, cache hierarchies, DMA engines, and storage interface controllers (NVMe, UFS, SD/eMMC).

Status

🚧 Reserved directory — Designs will be added in future releases.

Planned Modules

ModuleDescription
SimpleSRAMSingle-port SRAM wrapper with read/write arbitration
DualPortSRAMTrue dual-port SRAM with collision handling
SimpleCacheDirect-mapped cache with write-back policy
DMAEngineScatter-gather DMA with descriptor rings
AXI4SRAMBridgeAXI4-to-SRAM protocol adapter

Design Guidelines

  • Use rtlgen.ram for memory primitive instantiation
  • Maintain byte-enable granularity for sub-word writes
  • Consider read-latency vs combinational output trade-offs

See Also

  • ../fundamentals/SKILL.md — ram_demo.py basic usage

Security

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