chsier/adreader/ad-schematic-reader

Claude Code and agent skill by chsier/adreader

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Checking that the SKILL.md file is still in the repository.

Read verified Altium schematic connectivity from .PrjPcb projects or .SchDoc sheets through the bundled script-only Windows JSON runtime. Use when Codex needs to find sheets, components, pins, nets, or prove whether specified pins are connected. Do not use it for GUI automation, Altium Designer control, or circuit-function inference.

Install

npx vskill@latest install chsier/adreader/ad-schematic-reader

SKILL.md

AD Schematic Reader

Use the runtime as the only source for connectivity claims. It uses the fixed altium-monkey backend and does not require Altium Designer or a GUI.

Runtime

Set <runtime> to <skill-dir>\runtime\ad-schematic-reader-agent.exe. Use this bundled executable for normal Skill operation. It contains the parser runtime; do not require Python, pip, uv, Altium Designer, or GUI automation from the calling Agent.

Use source mode only when maintaining this Skill, not as a fallback for normal tasks.

Every command emits one JSON response on stdout. Prefer a .PrjPcb input; use a standalone .SchDoc only when no project is available.

Workflow

  1. Run inspect <input> and stop if its status is not pass.
  2. Run snapshot <input> --out <snapshot-dir> outside the source project directory.
  3. Run verify <snapshot-dir> before answering after any possible source-file change.
  4. Run summary, then a narrow component, net, or connection query.
  5. Answer only from the returned structured evidence.
powershell
<runtime> inspect <project-or-sheet> --pretty
<runtime> snapshot <project-or-sheet> --out <snapshot-dir> --pretty
<runtime> verify <snapshot-dir> --pretty
<runtime> summary <snapshot-dir> --pretty
<runtime> component <snapshot-dir> --designator U1 --sheet FPGA1.SchDoc --pretty
<runtime> net <snapshot-dir> --name USB2_STP --pretty
<runtime> connection <snapshot-dir> --designator U20 --pin 29 --sheet JTAG-USB.SchDoc --other-designator U1 --other-pin D20 --other-sheet FPGA1.SchDoc --pretty

Use components and nets with --limit and --offset for discovery. Use net --id after a name lookup if a display name is ambiguous. Pass the returned runtime net.id; it is deterministic for unchanged source inputs with this fixed Runtime.

Evidence Gate

  • State that two pins are connected only when status is pass, data.confirmed is true, and data.relation is connected.
  • State that one pin is connected or unconnected only when status is pass and data.confirmed is true.
  • Treat partial, unknown, not_in_source, and a stale snapshot as non-confirmation. Report the returned state and diagnostics instead of filling gaps.
  • Never infer a connection from matching net text, a filename, empty output, symbol appearance, or circuit knowledge.
  • Cite the returned source_file, sheet, designator, pin, net ID, and net name when present.
  • Do not infer circuit purpose or behavior. This skill proves connectivity only.

References

  • Read cli-api.md for exact command syntax, argument rules, and exit codes.
  • Read json-api.md before sending request payloads or integrating the runtime programmatically. The formal schemas are in schemas/v1.
  • Read data-contract.md for normalized snapshot entities and response evidence fields.
  • Read verification-rules.md before handling ambiguity, partial pin inventories, stale artifacts, or answer wording.
  • Read parser-backend.md for the fixed altium-monkey integration, supported inputs, and parser boundaries.
  • Read diagnostics.md when a command returns partial or fail.
  • Read runtime-package.md when copying, rebuilding, or distributing the bundled executable.

Security

  • Security scanPassed, 95 of 100Pattern checks on the skill's files.
  • Model reviewPassed

Quality evaluation

  • Task evaluationNot runNo evaluation yet. Run one in Skill Studio.

Source

Popularity

Repository stars
104
7-day trend score
23

Stars and forks are for the whole GitHub repository, not this skill alone. Not refreshed yet.

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