hdl-tools/digital-chip-design-agents/sta

Skill: Static Timing Analysis (STA)

Invocation

When this skill is loaded and a user presents a timing analysis task, do not execute stages directly. Immediately spawn the digital-chip-design-agents:sta-orchestrator agent and pass the full user request and any available context to it. The orchestrator enforces the stage sequence, loop-back rules, and sign-off criteria defined below.

Use the domain rules in this file only when the orchestrator reads this skill mid-flow for stage-specific guidance, or when the user asks a targeted reference question rather than requesting a full flow execution.

Pre-run Context

<MEM> below is the resolved memory root, never the literal memory/ directory: an explicit --memory-root, else $CHIP_DESIGN_MEMORY_ROOT, else the central default, else the in-repo seed (python3 plugins/infrastructure/skills/memory-keeper/memory_root.py prints it; the orchestrator's ## Memory section is authoritative).

Before executing or advising on any stage, read the following files if they exist:

1. <MEM>/sta/knowledge.md — known failure patterns, successful tool flags, PDK/tool quirks.

Incorporate its guidance into every stage decision. If absent, proceed without it.

1. <MEM>/sta/run_state.md — current run identity (run_id, design_name, tool,

last_stage). Use this to resume correctly after interruption. If absent, a new run is starting; the orchestrator will create this file before the first stage.

This pre-run read applies whether this skill is loaded by a user or called by the orchestrator mid-flow. It ensures the fix database is consulted before any diagnosis step.

Purpose

Multi-corner, multi-mode timing analysis, exception review, ECO-guided closure, and timing sign-off. WNS ≥ 0 and TNS = 0 at all corners required for tape-out.

Supported EDA Tools

Open-Source

• OpenSTA (sta) — standalone open-source STA; runs tcl scripts in batch mode (see sequential flow note below)
• OpenROAD STA subsystem (openroad -no_init) — STA within the OpenROAD PD flow; runs sequentially via tcl script

Proprietary

• Synopsys PrimeTime (pt_shell, dialect synopsys) — gold-standard multi-corner STA and power analysis
• Cadence Tempus (tempus, dialect cadence) — concurrent multi-mode multi-corner STA with ECO guidance;

optional, absent on some hosts — use PrimeTime there

• Synopsys StarRC (StarXtract, dialect synopsys) — extraction that produces the SPEF read here

(wrapper wrap-starrc.sh); the PD flow's extraction stage owns it

Sequential Flow Log Review (OpenSTA / OpenROAD STA)

OpenSTA (sta) and the OpenROAD STA subsystem (openroad -no_init) execute tcl script commands sequentially. When run in batch mode the agent must parse the output log to extract timing results — there is no interactive prompt to query mid-run.

Key log patterns to parse after run completion:

• report_timing output → extract WNS (worst negative slack) and critical path
• report_tns output → extract TNS (total negative slack) per corner
• report_clock_skew output → global skew and insertion delay per clock group
• check_timing → missing constraints, unconstrained endpoints, loops

Batch invocation:

opensta -no_splash -exit timing_check.tcl > sta.log 2>&1
# or via OpenROAD:
openroad -no_init -exit sta.tcl > sta.log 2>&1

Parse sta.log after completion. Apply loop-back rules (ECO guidance stage) if setup/hold violations are found.

Tool Notes: Synopsys PrimeTime (multi-corner) and PrimePower

Outline — measured notes pending. Process and standard command names only; no option recipe below has been verified on this suite's reference host yet. Run through wrap-pt.sh.

Multi-corner, one scenario per corner (DMSA or a single multi-scenario session):

1. Per corner: create_scenario (or one pt_shell per corner), then set link_path /

read_db the library .db of that corner, including every macro's .db

1. read_verilog + link_design the post-route netlist; read_sdc the one SDC every flow

shares (record its md5)

1. read_parasitics the SPEF of the RC corner mapped to that library corner (Cmax with

the slow library for setup, Cmin with the fast library for hold, unless the PDK's signoff table says otherwise) — write the mapping down; a scenario reading the wrong SPEF is the most common silent error

1. report_annotated_parasitics -check (or the version's equivalent) before any timing

report — see multi_corner_analysis annotation rule 2

1. update_timing, then report_qor, report_global_timing, `report_constraint

-all_violators, report_timing -delay_type max|min`

1. Collect WNS/TNS/violator count per scenario into one table; the corner set comes from

design_state.constraints.pvt_corners

PrimePower: set power_enable_analysis true, same netlist/SPEF/SDC as the timing scenario; read_saif/read_fsdb for vector-based power, otherwise vectorless with set_switching_activity default toggle rate and static probability on inputs; then update_power and report_power. Use the same activity assumption for every compared flow (the same default toggle rate, the same input activity, the same SAIF if any) and record it with the number; a power figure without its activity assumption is not comparable.

Fair Cross-Tool Comparison

When the timing or power of designs implemented by different tools is compared (for example Innovus vs ICC2 vs OpenROAD/LibreLane on one netlist and PDK), every flow is judged the same way, or the comparison measures the judges rather than the implementations:

1. Same SDC. Every flow reads the identical constraints file; record its md5 next to

each result (sta.sdc_md5). A tool-specific SDC variant is a different experiment

1. Same extractor and tech. Re-extract every flow's final DEF with one extractor and one

tech file at the same RC corners (extraction in the PD flow). A tool's built-in extraction is native

1. Same STA engine. Time every flow in one signoff engine and version (sta.engine),

with the same libraries, corners and derates

1. Same activity assumptions for power — the same vectorless defaults or the same SAIF
2. Native reports are recorded but labelled `native` (sta.judged_by). They are useful

for diagnosing a flow and are never ranked against another flow's signoff numbers

1. A comparison that cannot meet 1–4 (for example no common extractor tech) is reported as

indicative, with the unmet condition named

Stage: constraint_validation

Validation Checks

1. All clocks defined with correct period and waveform
2. All generated clocks: correct source and division/multiplication
3. No unconstrained paths: verify with report_timing -unconstrained
4. CDCs: correct false_path or max_delay applied
5. Multicycle paths: both –setup N and –hold 1 specified
6. Input/output delays: match system-level timing budget
7. Timing exceptions: not overly broad (masking real violations)
8. Propagated vs ideal clocks: correct mode (ideal pre-CTS, propagated post-CTS)

Common Constraint Errors

QoR Metrics to Evaluate

• 0 unconstrained paths
• 0 clock definition errors
• All exceptions reviewed and documented

Output Required

• Constraint QA report
• Clock summary (all clocks, sources, periods)
• Exception list with justifications

Stage: multi_corner_analysis

Required Corner Matrix

Corners are driven by design_state.constraints.pvt_corners[]. The table below shows the default corners used when pvt_corners is absent or contains no entries with non-null V/T:

When pvt_corners is populated, use every entry with "checks": ["setup"] for setup and every entry with "checks": ["hold"] for hold; the defaults above are the fallback.

POCV/AOCV Application

1. AOCV: apply depth and location-based derating (pre-POCV designs)
2. POCV: apply parametric variation (sigma-based, per foundry agreement)
3. Clock uncertainty: pre-CTS ideal values → post-CTS propagated

Annotation and engine rules

1. One scenario per corner, each reading its own library corner and the SPEF of the RC corner

mapped to it; record the mapping in the timing report header

1. Annotation gate. Before any slack is reported, read the annotation report

(report_annotated_parasitics, or the engine's equivalent): > 1 % of signal nets or any clock net unannotated is a FAIL of this stage (input_setup), whatever the slack says. An STA run on mostly unannotated nets reports clean timing that is false

1. Tempus may be absent; PrimeTime (pt_shell) or OpenSTA (sta) is then the engine. Name

the engine and version with every figure

Path Analysis Priority

1. WNS path per corner (most critical single path)
2. TNS contribution (how many paths fail and by how much)
3. CDC paths with max_delay constraints
4. At-speed paths: launch/capture pair STA

QoR Metrics — Sign-off Targets

Output Required

• Timing report per corner (setup and hold)
• WNS/TNS summary table across all corners
• Top 100 violating paths

Stage: path_analysis

Domain Rules

1. Group failing paths by root cause: long wire, weak driver, logic depth, high-Vt
2. Separate setup violations from hold violations — different fix strategies
3. At-speed violations: check launch/capture pair timing explicitly
4. False paths: verify every exception is still valid after PD changes
5. Reconvergent fanout: flag paths with reconvergence for careful ECO planning

Output Required

• Failing path analysis (root cause per path group)
• Paths requiring ECO vs paths requiring SDC correction

Stage: exception_review

Domain Rules

1. Review every timing exception for correctness and scope:

• set_false_path: verify the path is truly non-functional (not just inconvenient)
• set_multicycle_path: verify both -setup N and -hold 1 are set correctly
• set_max_delay: verify value matches system-level timing budget

1. Overly broad exceptions: any exception matching > 1% of all paths requires architect approval
2. Exceptions masking real violations: revoke immediately and re-run path analysis
3. Every exception must have a documented justification (design intent, async crossing, test mode)
4. Post-ECO exceptions: verify any new exceptions added after ECO are still valid

Common Exception Errors

QoR Metrics to Evaluate

• 0 exceptions without documented justification
• 0 overly broad exceptions (flagged for architect review)
• Exception list reviewed and signed off before ECO guidance begins