mohitmishra786/low-level-dev-skills/assembly-riscv
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RISC-V assembly skill for RV32/RV64 programming. Use when working with the RISC-V ISA, calling conventions (psABI), inline assembly with GCC/Clang, understanding extension naming (IMAFD), compressed instructions, or simulating RISC-V with QEMU and GDB remote debugging. Activates on queries about RISC-V assembly, RV32, RV64, RISC-V calling convention, RISC-V inline asm, RISC-V extensions, QEMU RISC-V, or RISC-V GDB.
Install
npx vskill@latest install mohitmishra786/low-level-dev-skills/assembly-riscvSKILL.md
RISC-V Assembly
Purpose
Guide agents through RISC-V assembly programming: RV32/RV64 instruction sets, register naming and calling conventions (psABI), ISA extension naming, inline assembly with GCC/Clang, compressed (RVC) instructions, and QEMU-based simulation with GDB remote debugging.
Triggers
- "How do I write RISC-V assembly?"
- "What are the RISC-V calling convention registers?"
- "How do I use inline asm for RISC-V in C?"
- "What do RISC-V extension letters mean (IMAFD)?"
- "How do I simulate RISC-V with QEMU?"
- "How do I debug RISC-V code with GDB?"
Workflow
1. Register file and calling convention
RISC-V has 32 integer registers (x0–x31) with ABI names:
| Register | ABI name | Role | Saved by | |
|---|---|---|---|---|
| x0 | zero | Hard-wired zero | — | |
| x1 | ra | Return address | Caller | |
| x2 | sp | Stack pointer | Callee | |
| x3 | gp | Global pointer | — | |
| x4 | tp | Thread pointer | — | |
| x5–x7 | t0–t2 | Temporaries | Caller | |
| x8 | s0/fp | Frame pointer | Callee | |
| x9 | s1 | Saved register | Callee | |
| x10–x11 | a0–a1 | Arguments / return values | Caller | |
| x12–x17 | a2–a7 | Arguments | Caller | |
| x18–x27 | s2–s11 | Saved registers | Callee | |
| x28–x31 | t3–t6 | Temporaries | Caller |
Floating-point registers (F extension): f0–f31 (fa0–fa7 for arguments).
2. Basic instructions
3. Minimal function (psABI calling convention)
4. ISA extension naming
RISC-V extensions are combined as a string after the base ISA:
| Letter | Extension | Description | |
|---|---|---|---|
| I | Integer | Base 32/64-bit integer (RV32I, RV64I) | |
| M | Multiply | Integer multiply and divide | |
| A | Atomic | Atomic memory operations (lr/sc, AMOs) | |
| F | Float | Single-precision float | |
| D | Double | Double-precision float | |
| C | Compressed | 16-bit compressed instructions | |
| G | General | = IMAFD (shorthand) | |
| V | Vector | Vector instructions (SIMD) | |
| Zicsr | CSR | Control/status register access | |
| Zifencei | Fence.i | Instruction-fetch fence | |
| Zba/Zbb/Zbc/Zbs | Bit manipulation | Bit ops (B extension set) | |
| Ztso | TSO | Total Store Ordering memory model |
Common targets:
- Embedded:
rv32imac— no floating point, with atomics and compressed - Linux app:
rv64gc— full general + compressed - High performance:
rv64gcv— + vector
5. Inline assembly (GCC/Clang)
6. Compressed instructions (RVC)
RVC replaces common 32-bit instructions with 16-bit versions when:
- Register is in x8–x15 (for
c.versions) - Immediate fits in smaller field
- Specific instruction patterns match
7. QEMU simulation and GDB
For the RISC-V psABI calling convention details, see references/riscv-abi.md.
Related skills
- Use
skills/low-level-programming/assembly-armfor AArch64 comparison - Use
skills/low-level-programming/assembly-x86for x86-64 assembly - Use
skills/embedded/openocd-jtagfor real hardware RISC-V debugging - Use
skills/compilers/cross-gccfor RISC-V cross-compilation setup
Security
- Security scanPassed, 100 of 100Pattern checks on the skill's files.
- Model reviewPassed
Quality evaluation
- Task evaluationNot runNo evaluation yet. Run one in Skill Studio.
Source
- SKILL.md in the repositoryCheckingskills/low-level-programming/assembly-riscv/SKILL.md
Popularity
- Repository stars
- 237
- Repository forks
- 28
- 7-day trend score
- 27
Stars and forks are for the whole GitHub repository, not this skill alone. Not refreshed yet.
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