xilinx/ross-ai-assistant/segcfg-aie

Explain how AI Engines interact with Segmented Configuration and guide the user through the combined AIE + segmented config design and build flow.

Instructions

1. Explain AI Engine configuration partitioning in a Segmented Configuration design:

• The AIE configuration path and config tile (PLL, clocking) go into boot.pdi
• The AIE array configuration and core ELFs are packaged with pl.pdi into pl_aie.pdi
• An AIE-only PDI can be separately packaged and loaded after pl.pdi if needed

1. Explain XSA export considerations:

• The design must include the AI Engine and its NoC configuration path
• write_hw_platform automatically generates a Segmented Configuration extensible XSA
• No additional flags needed — the segmented nature is detected from the project property

1. Explain the Vitis v++ Hardware Flow:

• boot.pdi: build and configuration steps are identical to the standard (non-segmented) Vivado flow
• pl_aie.pdi: build and load process is the same as the standard Vitis flow
• xclbin: Vitis metadata generated by the v++ packager; host application reads it identically to a non-segmented design
• No special v++ flags are needed to support Segmented Configuration

1. Explain the Vitis v++ Hardware Emulation (HW_EMU) Flow:

• HW_EMU focuses on simulating application execution, not PDI configuration behavior
• Compatible with Segmented Configuration-enabled designs without modification
• Pre-loads PL contents using RTL simulators (no runtime PDI loading in emulation)
• Dynamically loads AIE configuration using fpgautil aie_pl.pdi, but ignores PL configuration data (already pre-loaded by simulator)
• Host application reads xclbin metadata the same way as in the hardware flow

1. Provide design guidance for AIE + Segmented Configuration:

• Ensure the NoC path connecting PS to the AIE configuration tile has initial_boot = true set
• This ensures the AIE config tile is initialized in boot.pdi so the array is ready when pld.pdi loads the ELFs
• Verify and set the NoC initial_boot paths in Vivado before implementation
• Validate with /segcfg-design-check — run SEGCONFIG DRCs to confirm AIE NoC paths are correct

1. For AIE + PL Reload scenarios:

• The AIE configuration tile (in boot.pdi) remains constant across PL reload operations
• AIE array configuration and ELFs (in pl_aie.pdi) can change with each PL variant
• The golden design must establish the full AIE NoC path superset (same rule as PL boundary)
• Import the NoC solution file from the golden run before compiling AIE variants

1. Reference documentation:

• UG1701: Vitis AI Engine documentation covering Segmented Configuration + AIE emulation flow details
• Use Vivado write_device_image to produce boot.pdi and pl_aie.pdi

1. Ask the user which part of the flow they need help with:

• Setting up the design with AIE included
• Exporting XSA for Vitis
• Building with v++ for hardware or emulation
• Running PL reload with AIE variants